Implementation of a PCI Bus Target Interface in a High Density FPGA

Today’s designs have grown in size and complexity by orders of magnitude in comparison to common designs of only a few years ago. FPGAs have also grown in size and density, with 100k-gate FPGAs now available. Because of this growth in FPGA density, designs that previously required an ASIC implementation may now be targeted to an FPGA. However, schematic based design is no longer the ideal method of design entry when attempting to meet time-to-market requirements. Hardware Description Languages (HDLs) such as VHDL and Verilog are necessities for high speed design targeting high density FPGAs. Because of the need for HDLs, HDL synthesizers play a vital role in the design process. Moreover, once placeand-route of the design has been completed, FPGA level and system level timing verification become critical design paths. This paper analyzes the entire design process required to implement a high complexity, high speed design a Peripheral Component Interface (PCI) Bus Target Controller Interface in a high density FPGA. Selection of a design methodology will be discussed as well as the ramifications of this choice in regards to the selection of a suite of tools for performing design entry and analysis and the selection of the target technology. The design process will be examined and common problems that were encountered will be discussed as well as the implemented solutions. Finally, design performance will be analyzed based on maximum frequency of operation, ease of system level integration and analysis, as well as time and effort required to complete the design process. I. PCI Bus Target Controller Interface Requirements As detailed in [13], a PCI Bus Target Controller Interface has the following critical design parameters at the FPGA level: Maximum clock rate of 33 MHz. Minimum input set up time to clock of 7 ns. Minimum hold time from clock of 0 ns. Maximum clock to signal valid delay of 11 ns. 36-bit parity generation and checking for I/O, memory, and configuration spaces. 36-bit input and output pipelines. 48 PCI bus connections and 70+ back end connections. Full-speed burst support in memory space. PCI interrupt support. PCI configuration space registers for device ID, vendor ID, status, command, class code, revision ID, memory base address, I/O base address, interrupt line, and interrupt pin. As detailed in [13], a PCI Bus Target Controller Interface has the following critical design parameters at the system level: AC output drive characteristics defined as I/V curves for minimum and maximum drive current. Maximum input pin capacitance of 10 pF. Maximum leakage current of 70 nA. II. Design Methodology As design complexity and speed increase, the complexity of the targeted FPGA’s architecture must also increase. A schematic based design methodology is incapable of supporting this increase in FPGA architectural complexity. Therefore, a language based design methodology was used to implement the PCI Bus Target Controller Interface. Language based design, originally a design methodology reserved for ASIC targets[3], is performed at a higher level of abstraction than schematic based design and is therefore geared toward more complex design solutions. As stated in [2], this method of designing at a higher level of abstraction, also known as top-down design, is more efficient than the traditional methodology of bottom-up design, where lower implementation levels are designed and verified before connected to the higher levels of the design. Changes to the design are far easier to implement and evaluate at this higher level of abstraction and result in minor implementation changes at the lower levels, therefore decreasing the length of the design cycle. Language based design is more conducive to partitioning of the design into submodules in a hierarchical manner, allowing for more efficient design management[4]. Hierarchical design also results in a hierarchy of functions that allow for simulation of submodules and a comp arison of the results with higher level behavioral descriptions. This process yields accurate predictions of a design’s performance prior to place-and-route[2]. Finally, HDLs allow for the development of designs that are independent of the target technology. As stated in [7], for high density designs, it is more efficient and error-free to create and verify designs at a technologyindependent level. However, through the use of an intelligent synthesizer, technology specific solutions are possible. Many vendors provide technology-specific and optimized implementations an intelligent synthesizer will take advantage of these implementations to yield a design that is optimized for area and speed[5]. Synthesis tools also allow for the integration of the modeling, verification, and implementation processes. The same HDL code can be used for verification and implementation, reducing code maintenance and the risk of inconsistencies between models[6]. III. Selection of the Design Tool Suite Because of the choice of a language based design methodology, a high performance tool suite was required to allow for optimal implementation of the design. The chosen tool suite had to allow for HDL design entry, architectural synthesis, and preand post-route simulation. The synthesis tools had to provide architecture specific optimizations and design implementations at the FPGA level as part of the design flow. These architecture specific optimizations and implementations would result in the synthesis of a design that is efficient in its usage of area in the FPGA as well as maximizing the speed capability of the design. At the system level, tools that allow for the evaluation of signal integrity and static timing analysis were a necessity when analyzing board level interconnection delays and cross-talk between signals. Automation of the design flow as well as ease of use of the individual point tools was also considered while selecting a suite of tools[1]. Finally, the tool suite had to be fully integrated with all FPGA vendor tools to guarantee a smooth design flow. In the past, most language based design was performed in a UNIX environment and targeted toward ASICs. However, due to the decrease in cost and the increase in performance of today’s PCs, as well as the availability of vendor placeand-route tools for the PC environment, the choice was made to design in the PC environment, necessitating a PC-based tool suite that may be used in both the Windows NT and Windows95 operating systems. The tool suite chosen for design development was WorkView Office, provided by Viewlogic Systems, Inc. WorkView Office provides a suite of tools that satisfied the design entry, synthesis, simulation, and automation requirements, both at the FPGA level and the board level. ViewSynthesis was used for synthesis of the HDL design. Digital Fusion was used for all phases of simulation at the FPGA level due to its support of both HDL and gate level simulation. Motive was used for board level static timing analysis and XTK was used for board level signal integrity analysis. Finally, IntelliFlow was used to automate the design flow, allowing for concentration on the design itself rather than on the tool interfaces[1]. IV. Selection of the Target Technology FPGA architectural granularity is extremely important in evaluating possible target technologies. Fine-grained architectures employ simple transistor-level elements while coarsegrained architectures involve multiple transistors implemented in pre-wired blocks. Generally, the more fine-grained the architecture, the more ASIC-like the FPGA[8]. The importance of granularity is obvious the more ASIC-like architecture will generally yield better synthesized results from the HDL code since language based design was originally created for ASIC targets. Another important factor in selecting a target technology is FPGA density, which is defined in terms of usable gates. Many FPGA vendors list the number of total gates available for a given FPGA. However, the true indication of an FPGA’s density is in terms of usable gates. The number of usable gates is determined by the effectiveness of the vendor’s place-and-route tools, and is defined as the percentage of the total gates available that the place-and-route tools can successfully route. As an FPGA’s usable gate count increases, there is a resulting increase in design performance in respect to both routability and speed. I/O capacity is also a deciding trait when choosing an FPGA. While more I/O is always desirable, the obvious tradeoff occurs in board space. Selecting an FPGA with increased I/O capacity results in a corresponding increase in package size and hence the amount of board space required. Normally, the physical size of the FPGA would be an important criteria for device selection. However, no limitation on available board space was given as a design requirement, therefore eliminating the issue of fitting the FPGA into a specified area in the system. In designs where board space is limited, it is important to remember that the I/O capacity of the FPGA is greatly affected by the package type selected. The PCI Bus Target Controller Interface requires 123 I/O pins. On-chip RAM is another extremely useful feature available on some FPGAs. On-chip RAM has faster access times than off-chip RAM and does not require the extra board space for off-chip RAM. If on-chip RAM is not present, the only available method for implementing RAM within the FPGA is to use the flip-flops that implement gate level functions as look-up tables (LUTs) in logic elements (LEs). However this underutilizes the LEs and results in poor overall FPGA utilization. Table I lists usable gates, maximum I/O, and on-chip RAM bits available for four FPGA vendors. Data is from [8], [9], [10], and [11] and is displayed for equivalent FPGAs that meet the minimum I/O requirement of the PCI Bus Target Controller Interface. Data for the Actel A32200DX, Lucent OR2C15A, and Xilinx XC4013E are for 208 pin quad flat pack (QFP) packages. Data for the Altera EPF81500 is for a 240 pin QFP package.